Search results for "Instructions per cycle"
showing 2 items of 2 documents
Exploiting selective instruction reuse and value prediction in a superscalar architecture
2009
In our previously published research we discovered some very difficult to predict branches, called unbiased branches. Since the overall performance of modern processors is seriously affected by misprediction recovery, especially these difficult branches represent a source of important performance penalties. Our statistics show that about 28% of branches are dependent on critical Load instructions. Moreover, 5.61% of branches are unbiased and depend on critical Loads, too. In the same way, about 21% of branches depend on MUL/DIV instructions whereas 3.76% are unbiased and depend on MUL/DIV instructions. These dependences involve high-penalty mispredictions becoming serious performance obstac…
Optimizing the Integration Area and Performance of VLIW Architectures by Hardware/Software Co-design
2021
The cost and the performance are major concerns that the designers of embedded processors shall take into account, especially for market considerations. In order to reduce the cost, embedded systems rely on simple hardware architectures like VLIW (Very Long Instruction Word) processors and they look for compiler support. This paper aims at developing a design space explorer of VLIW architectures from different perspectives like processing performance and integration area. A multi-objective Genetic Algorithm (GA) was used to find the optimum hardware configuration of an embedded system and the optimization rules applied by compiler on the benchmarks code. The first step consisted in represen…